This paper introduced and desinged an interface circuit by means of large scale integrated circuit PMM8713.
介紹了用大規(guī)模集成電路PMM871 3設(shè)計(jì)的控制和驅(qū)動(dòng) 3相、4相步進(jìn)電機(jī)的通用步進(jìn)電機(jī)接口電路 。
A compilation/generation method for test program of large scale integrated circuit (LSI), called Fault Simulation Method is presented in this paper.
本文敘述了一種名為故障模擬法的大規(guī)模集成電路的測(cè)試程序的編制、生成方法，這種方法主要是解決了隨著大規(guī)模集成電路的發(fā)展，單個(gè)電路本身的輸入／輸出管腳數(shù)量不斷增加，帶來(lái)測(cè)試矢量呈現(xiàn)指數(shù)增長(zhǎng)，從測(cè)試時(shí)間和測(cè)試成本上考慮，使用傳統(tǒng)的窮舉法已經(jīng)不可能編制、生成出符合要求的大規(guī)模集成電路測(cè)試程序的問(wèn)題。
Research on Parallel Seam Sealing Process for LSI;
大規(guī)模集成電路的平行縫焊工藝研究
A kind of super purification control system which can realize the high spotless environment for LSI s manufacturing is introduced.
介紹了一種實(shí)現(xiàn)大規(guī)模集成電路 (LSI)無(wú)塵生產(chǎn)環(huán)境的超凈化控制系統(tǒng) ,該系統(tǒng)的現(xiàn)場(chǎng)控制回路采用了先進(jìn)的仿人工智能PID控制算法 ,這種算法避免了系統(tǒng)反饋滯后的振蕩缺陷 ,利用LonWorks的網(wǎng)絡(luò)技術(shù) ,實(shí)現(xiàn)整體凈化系統(tǒng)的智能化、可視化控制。
The method will make the circuit more terse and reliable by using the LSI is pLSI1016 chip of lattice corporation as the core.
介紹了一種基于FPGA芯片設(shè)計(jì)FSK調(diào)制解調(diào)器的基本原理,并給出相應(yīng)的VHDL語(yǔ)言描述,該設(shè)計(jì)以Lattice公司的大規(guī)模集成電路ispLSI1016芯片為核心,使得電路簡(jiǎn)潔、可靠性高。
Our algorithm not only avoids polynomial deflation but also is more efficient than traditional rootfinding algorithm and it is fit for being realized by VLSI.
該算法避免了多項(xiàng)式降次,計(jì)算量又遠(yuǎn)遠(yuǎn)小于經(jīng)典的搜索算法,適于用大規(guī)模集成電路實(shí)現(xiàn),而且可以推廣應(yīng)用于求解更高階LSF參數(shù)。
With the appearance of VLSI ATE,Auto test technology has been wide used,So production of IC validation is efficiency,This paper has introduced the typical flow of test in IC electric parameter,Then explain the basic principle of test and imaginable result.
隨著大規(guī)模集成電路自動(dòng)測(cè)試設(shè)備的出現(xiàn),自動(dòng)測(cè)試技術(shù)被廣泛應(yīng)用,實(shí)現(xiàn)了高效率的集成電路產(chǎn)品驗(yàn)證,這就使得應(yīng)用自動(dòng)測(cè)試設(shè)備有了一定的流程。
With the development of VLSI(Very Large Scale Integration), the integrity becomes larger and larger, from hundreds of thousand to millions or tens of millions, and it becomes more difficult to finish the verification task.
隨著大規(guī)模集成電路的發(fā)展,其設(shè)計(jì)規(guī)模不斷增加,從幾十萬(wàn)門級(jí)發(fā)展到百萬(wàn)、千萬(wàn)門級(jí),完成相應(yīng)的驗(yàn)證工作也變得越來(lái)越困難,給相應(yīng)的驗(yàn)證工作帶來(lái)了巨大的挑戰(zhàn)。
Test methods of total dose effects in very large scale integrated circuits;
大規(guī)模集成電路總劑量效應(yīng)測(cè)試方法初探