However, they lack ASIC - level performance because of their generalized architectures.
然而, 由于它們采用歸一化的體系結(jié)構(gòu),故缺乏ASIC檔次的性能.
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Partial dynamic reconfiguration system is unrivalled by ASIC and statically configuring FPGA.
其中的局部動態(tài)重配置系統(tǒng)有著ASIC以及靜態(tài)配置FPGA無法比擬的優(yōu)勢.
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Hands - on experience in ASIC design and system modeling.
有ASIC設(shè)計(jì)和系統(tǒng)建模的經(jīng)驗(yàn).
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Because of the complexity of SDH, ASIC is the trend of the evolution.
由于SDH設(shè)備 的復(fù)雜性, SDH專用集成電路(ASIC) 的設(shè)計(jì)使用就成為SDH發(fā)展 的必然趨勢.
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It'still produces sensor of sensor of ASIC, optical image, optical position, LED and optocoupler product.
它還出產(chǎn)ASIC 、 光學(xué)圖像傳感器 、 光學(xué)地位傳感器 、 LED和光耦合器產(chǎn)物.
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A lot of main ASIC manufacturer transfer standard unit and built - in array smoothly.
許多主要的ASIC廠家都順利地轉(zhuǎn)移到標(biāo)準(zhǔn)單元和嵌入陣列.
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One feature of SOC design , which is very different with ASIC design, is IP reusability.
SOC不同于普通ASIC的特點(diǎn)之一, 即為其IP可重用性.
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For cost reduction and integration, this glue logic was often swept digitalintegrated circuit ( ASIC ) .
為了降低成本實(shí)現(xiàn)一體化, “黏合邏輯”曾經(jīng)風(fēng)靡整個(gè) ASIC 業(yè).
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This is a surface - installation type package used for the ASIC for industrial and communications equipment.
使用在工業(yè)設(shè)備或通信設(shè)備等ASIC上面 的表面貼裝用基座.
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The paper designs a reliable smart home network system using programmable ASIC device as core device.
本課題是研究利用可編程ASIC器件為核心器件設(shè)計(jì)性能可靠的家庭智能網(wǎng)絡(luò)系統(tǒng).
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Two alternative approaches to classic ASIC - centered and DSP - assisted architectures have emerged andand accelerator - assisted architectures.
于是,出現(xiàn)了兩種可供選擇的辦法:用傳統(tǒng)的ASIC為主DSP為輔的結(jié)構(gòu)替換上述結(jié)構(gòu).
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RCT Receiver ASIC is the core of Radio - controlled timekeeper.
電波表的核心器件是接收芯片.
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This paper mainly discusses the test of digital ASIC.
本文主要討論了數(shù)字專用集成電路的檢測.
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ASIC design follows the steps as described below : system design → logic design → circuitdesign → mask design → technology design.
專用集成電路的正向設(shè)計(jì),需依次經(jīng)歷如下一些設(shè)計(jì)步驟: 系統(tǒng)設(shè)計(jì)→邏輯設(shè)計(jì)→電路設(shè)計(jì)→版圖設(shè)計(jì)→工藝設(shè)計(jì).
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A new adaptive frame rate up conversion algorithm and its ASIC design television are presented.
提出一種隔行到逐行自適應(yīng)幀頻提升算法和該算法的芯片設(shè)計(jì)方法.
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